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Technical Paper • December 2025

MultiTab-Core-T: Compressed Decision ASIC for Planetary Rovers

A hybrid ASIC architecture combining a tiny Transformer context engine with tabular MLP experts, enabling ultra-low-power autonomous decisions for planetary rovers under extreme resource constraints.

December 2025
Ing. Jose Luis Minich • Tab-Core Labs
7 pages • Architectural Study
Analytical Estimates (Not Measured Silicon)

Architecture Overview

High-level architecture: Tab-Core-T encodes tabular inputs into an embedding e, which is broadcast to a MultiTab Fabric of expert MLP cores and aggregated into final scores.
Figure 1: Data flow through the MultiTab-Core-T architecture. Tab-Core-T encodes tabular inputs into a context embedding e, which is broadcast to a MultiTab Fabric of expert MLP cores. Their outputs are fused into final scores.

MultiTab-Core-T is a specialized ASIC architecture designed for safety-critical decision-making on planetary rovers, where power budgets (few watts), radiation tolerance, and communication delays (minutes to tens of minutes) make deploying large AI models impractical. The architecture combines two core components: (1) a tiny Transformer-based context engine that encodes short state and event histories, and (2) an array of efficient tabular MLP cores that evaluate trajectory risk, energy costs, and anomaly scores from numeric sensor features.

System Integration

Host System
Host CPU
System Memory
PCIe / high-speed link
Tab-Core PCIe Card
Power
Regulators
Optional
Card DRAM
Tab-Core ASIC
RISC-V Control & Runtime
On-chip Weight Memory
MLP Core Array
Typical power: ~1.5 W (core) + board overhead
Scores /
Inference Results

Figure 2: System-level integration showing the host CPU, PCIe link, Tab-Core card with power regulators, and the ASIC containing RISC-V control, weight memory, and MLP core array

Rather than running large models on-board, we propose a teacher–student compression framework: high-capacity teacher models on Earth (LLMs, physics simulators, vision backbones) generate training targets over extensive rover scenarios; a compact on-board student ensemble approximates their decisions within the mission's operational envelope. The resulting system targets sub-millisecond latency and sub-watt power consumption.

This paper presents the architectural design, analytical performance and energy modeling (not measured silicon), and a roadmap toward aerospace-grade implementation. The same principles apply to terrestrial high-throughput decision workloads where tabular features and short context dominate—including online advertising, recommender systems, and financial risk scoring.

Keywords
ASIC architecture Planetary rovers Knowledge distillation Tabular ML Edge AI Low-power inference

📄 Download Technical Paper

Full architectural study (7 pages) including detailed system design, analytical performance modeling, energy estimates, and comparisons with CPU/GPU baselines. All 20 references included in the PDF.

For academic use: LaTeX source also available